Apparatus for producing a signal when a selected phase relationship exists between two alternating current voltages of different frequencies

ABSTRACT

A signal is produced when a selected phase relationship exists between two alternating current voltages of different frequencies by converting the alternating current waveforms to square waves, combining the square waves to produce a rectangular waveform, and utilizing the rectangular waveform to produce a triangular beat frequency signal having a linear relationship between phase difference and time, and a level detector has the triangular beat frequency signal applied thereto and produces an output signal when the triangular beat frequency signal exceeds in amplitude a selected level in the level detector.

States tat ite Rubner et al.

APPARATUS FOR PRODUCING A SIGNAL WHEN A SELECTED PHASE RELATIONSHIP EXISTS BETWEEN TWO ALTERNATING CURRENT VOLTAGES OF DIFFERENT FREQUENCIES Inventors: Tibor Rubner, Pittsburgh; Andre Wavre,

Monroeville; John H. Bednarek, Murrysville, all of Pa.

Assignee: Westinghouse Electric Corporation, Pittsburgh, Pa.

Filed: Dec. 23, 1969 Appl. No.: 889,824

Related US. Application Data Division of Ser. No. 695,684, Jan. 4, 1968.

US. Cl. ..324/82, 324/83 A Int. Cl ..G0lr 23/00, G011" 25/00 Field of Search ..324/83 A, 83 D, 82; 328/133;

[56] References Cited UNITED STATES PATENTS 3,441,862 4/1969 Mitchell ...328/l33 X OTHER PUBLICATIONS Yu; Proc. Nat. Elec. Conf., Vol. 16; 1961; pp. 677- 684.

Primary Examiner-Alfred E. Smith Attorney-A. T. Stratton, C. L. McI-Iale and M. l. Hull [5 7] ABSTRACT 6 Claims, 7 Drawing Figures P'ATiNTfnmzaler 3.652.983

SHEET 1 OF 5 m (I06 k glen Wm us, 3 10a gm 7 I23) I04 1 rll ai 24 FIG. IA.

,131 70s FLIP A m FLOP 7'07 FLIP m FLOP FIG. 2A

INVENTORS Tibor Rubner, Andre Wuvre John H. Bednorek ATTORNEY PATENTEIJMAR28 I972 I 3,652,933

SHEET 3 OF 5 693 l l 30! OR LEVEL PULSE 620 De ECTOR 1':

Bus SHAPER MIXER AND EQQY- PULSE LTER SHAPER E I GENERATOR SQUARED BUS VOLTAGE f [SQUARED GENERATOR VOLTAGE 1Sl 's2s|"s2 i F DISCRIMINATING LEVEL DEFINITE TIME r-SYNCHRONISM FIG 4.

PATENTEDMAR28 1972 3,652,933

SHEET u [If 5 APPARATUS FOR PRODUCING A SIGNAL WHEN A SELECTED PHASE RELATIONSHIP EXISTS BETWEEN TWO ALTERNATING CURRENT VOLTAGES OF DIFFERENT FREQUENCIES This application is a division of copending application Ser. No. 695,684, filed Jan. 4, 1968, titled Automatic Generator Synchronizing and Connecting System and Synchronizer Apparatus for Use Therein, and owned by the present assignee.

CROSS-REFERENCE TO RELATED APPLICATIONS A voltage acceptor including the overvoltage-undervoltage detector employed with the present system is shown, described, and claimed in the copending application of Tibor Rubner for Voltage Acceptor Circuit and Overvoltage-Undervoltage Detector For Use Therein, Ser. No. 695,020, filed Jan. 2, 1968. The generator speed matcher employed in the present system is shown, described, and claimed in the copending application of Francis T. Thompson and Tibor Rubner for Generator Speed Matcher Using Direct Sampling, Ser. No. 695,021, filed Jan. 2, 1968, now U.S. Pat. No. 3,553,596. The voltage matcher employed in the system is described and claimed in the copending application of Tibor Rubner et al. for Solid State Voltage Matcher and Voltage Difference Detector for Use Therein, Ser. No. 695,026, filed Jan. 2, 1968. All of the aforementioned copending applications are assigned to the assignee of the instant invention.

BACKGROUND OF THE INVENTION l. Field of the Invention The invention relates to a system and apparatus for ascertaining the voltage relationships between a bus and an oncoming generator to be connected in parallel with the generator exciting the bus, for ascertaining the magnitudes and relative frequencies of the voltages and the phase relationships and creating the necessary voltage and frequency relationships and connecting the generator to the bus at the proper instant. Such devices are generally referred to as synchronizers although additional circuitry may be employed.

2. Description of the Prior Art As previously stated it is generally necessary to compare the phases of the two voltages, and one patent directed to a phase detector is titled Phase Detector Using Zener Diode Bridges and a Summing Network," U.S. Pat. No. 3,213,362, issued Oct. 19, 1965 to S. D. Silliman et al. U.S. Pat. No. 3,069,555 is for an Automatic Paralleling System," issued Dec. 18, 1962 to L. L. Kessler The literature of the art describes several prior art automatic synchronizing equipments, including an article titled Automatic Check Synchronizing Equipment Using Static Relaying Principles by C. Adamson and O. P. Mosland, The Institution of Electrical Engineers, Paper No. 3567, Aug. 1961; and an article titled Automatic Control of Hydroelectric Generating Stations" by M. J. Brown and W. A. Derr, AIEE Transactions, Vol. 66, 1947, pp. 343-355.

SUMMARY OF THE INVENTION The system includes a voltage acceptor having the bus voltage and the generator voltage applied thereto, includes an overvoltage-undervoltage detector, which, selectively, according to the embodiment thereof employed, provides an output signal (the DC supply voltage or a portion thereof) when the voltages of the bus and generator are sufficiently close so that the generator may be connected to the bus, or according to another embodiment thereof supplies a lockout signal when the generator and bus voltages are not sufficiently close for the generator to be connected to the bus. When the two voltages are sufficiently far apart and differ sufficiently from a center voltage so that the generator may not be connected to the bus, a lockout signal is applied to a synchronizer, disabling the synchronizer and preventing an output signal from the synchronizer which would close a circuit breaker or breakers to connect the generator to the bus.

Further, a converter circuit is employed having the bus and generator voltages applied thereto, the converter circuit providing a squared bus voltage and a squared generator voltage which are applied to a speed matcher circuit, and further the converter creates a phase difference signal which is applied to both the speed matcher circuit and the synchronizer. The speed matcher circuit generates in the alternative a decrease speed signal or an increase speed signal depending upon the frequency relationship of the bus and generator voltages. Further, a voltage matcher circuit is employed having the generator and bus voltages applied thereto for alternatively generating a raise" voltage signal or a lower voltage signal. When all of the conditions exist for proper shunt connection the synchronizer circuit supplied anenergizing current to the circuit breaker a predetermined time in advance of the correct place condition, in accordance with the intrinsic closing time of the circuit breaker.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A and 1B taken together are a block diagram of the complete system showing the units thereof, i.e., the voltage acceptor, converter, synchronizer, voltage matcher, and speed matcher, and the various controls of a major nature employed by an operator of the system.

FIGS. 2A and 2B are block diagrams of the synchronizer unit of the system.

FIGS. 3A and 3B taken together comprise a schematic electrical circuit diagram of the converter and synchronizer.

FIG. 4 is a series of graphs or curves illustrating the operation of the synchronizer and the converter.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Particular reference is made now to FIGS. 1A and 1B. The block generally designated 16 is a voltage acceptor including an overvoltage-undervoltage detector, as described and claimed in the copending application of Tibor Rubner, Ser. No. 695,020, filed Jan. 2, 1968, and assigned to the assignee of the instant invention. In that copending application, two schematic circuit diagrams suitable for use in the block 16 are shown, one of these schematic electrical circuit diagrams including two variable resistors, or potentiometers, one for adjusting the value of the base or center" voltage at which it is desired synchronization take place, for example, at a selected value between and 125 volts, for example 120 volts, and one of these potentiometers adjusting the range, or the tolerance from the base voltage, at which connection may be made, this range being for example from 0 to 20 volts. The respective variable resistor controls are indicated at 17 and 18. The leads l9 and 20 are connected to the secondary 117 of a potential transformer generally designated the primary of which is connected across one phase of the generator, conductors 107 and 108. Leads 21 and 22 are connected to the secondary 118 of a potential transformer generally designated 116 the primary of which is energized from a corresponding phase of the bus, conductors 112 and 113. The output signal of the voltage acceptor is developed on lead 23 with respect to ground 24, and lead 25 is connected to the positive terminal of a source of direct current potential which may be 50 volts with respect to ground. The source of potential is not shown for simplicity of illustration.

There is shown at 26 a converter block, a schematic electrical circuit diagram of which is shown in a portion of FIG. 3A. Leads 19 and 20 are connected to the generator transformer, and leads 21 and 22 are connected to the bus transformer. By way of output leads 31, 32, and 33, three signals are supplied from the converter to a speed matcher circuit indicated by block 38; The signal on lead 31 may be a squared generator voltage obtained from terminal 41 in FIG. 3A. The signal on lead 32 may be a squared bus voltage obtained from terminal 42, FIG. 3A, and the signal on lead 33 is a composite signal representative of the phase relationships between the bus and generator voltages and may be obtained from terminal 43,

FIG. 3A. Leads 34 and 35, FIG. 1A may be +40 volt and +12 volt supply leads, and may correspond to leads 686 and 434 respectively, FIGS. 3A-3B.

Synchronizer 50 has output leads 53 and 54 connected to the winding 55 of a relay generally designated 56, which winding when deenergized causes armature 57 to close a circuit between lead 53 and lead 58, and as will be seen from FIGS. 3A-3B, +50 volts is applied to lead 53 through an RC filter, lead 52 and armature 48. Lead 51 is connected to the +50 volt supply through armature 47 and lead 49. Armature 47 represents a normally open auxiliary contact of circuit breaker 100 and provides intelligence needed for preventing circuit breaker pumping as will be more fully described hereinafter. Lead 52 is seen to be connected to the +50 volt supply through armature 48. Armature 48 represents a normally closed auxiliary contact of circuit breaker 1110. This last mentioned auxiliary contact is used to disable the synchronizer and stop speed matching and voltage matching actions once circuit breaker 100 is closed. The synchronizer 50 is seen to include three controls shown at 44, 45, and 46. Control 44 is an advance angle control, which may correspond to potentiometer 561, FIG. 3B, and be calibrated in a range from (L40 degrees. Control 46 is a breaker closing time control and, may correspond to potentiometer 380, while multiplier 45 may correspond to switch arms 383 and 384, and capacitors 391 and 392, FIG. 3B.

The operation of the aforementioned speed matcher 38 will be more fully explained hereinafter, and still more fully explained in the aforementioned copending patent application. It is seen however to have output leads 61, 62, 63, and 64, leads 61 and 62 being connected to winding 65 of a relay generally designated 66 having armatures 67 and 68, armature 67, when the circuit is closed therethrough, connecting lead 63 to lead 58 which is connected to +50 volts through armature 57, aforementioned filter contained in block 50, lead 52 and armature 48. Leads 63 and 64 are connected across winding 71 of a relay generally designated 72 having armatures 73 and 74, the circuit when closed through armature 73 connecting lead 61 to lead 58 which is connected to +50 volts as aforementioned.

The system of FIG. 1A-1B also includes a voltage matcher shown at block 26, having controls 77 and 78 which include a voltage difference adjustment and a pulse duration control. A suitable voltage matcher is described and claimed in the copending patent application of Rubner and Bednarek. Input leads l9 and 20 are connected to the generator transformer and input leads 21 and 22 are connected to the bus transformer. Power supply lead 83 is connected to the positive terminal of a source of potential, not shown for convenience of illustration, which may be of the order of 50 volts having the negative terminal thereof connected to ground. Output leads 85 and 86 are connected to the winding 89 of a relay generally designated 90 having armatures 91 and 92. Armature 91, when the circuit is closed therethrough, connects output lead 87 to the aforementioned lead 58 which is connected to +50 volts as aforementioned. The aforementioned output lead 37 and output lead 88 are connected to winding 94 of a relay generally designated 95 having armatures 96 and 97. Armature 96, when the circuit is closed therethrough, connects lead 85 to the aforementioned lead 58 which is connected to +50 volts in the aforementioned manner.

When synchronizer 50 energizes the winding 55 of relay 56, the circuit is closed through armature 120, by way of lead 122, to energize breaker closing coil 104 from source 123.

It is seen that the circuit breaker generally designated 100 has three contact circuit closing members or armatures 1111, 102, 103 which operate together when winding 104 is energized to connect three phase lines 1116, 107, and 108, which are connected to the oncoming generator, to energized buses 1 11, 1 12, and 113 respectively. As aforementioned, two single phase potential transformers are shown at 115 and 116, the primary of transformer 115 being connected across a selected phase of the three phase generator, in the illustration shown the phase of conductors 107 and 108, and the primary of the other potential transformer 116 is connected across the corresponding phase of the three phase bus, in this case across conductors 112 and 113. Secondary 117 of transformer provides a voltage which varies with variations in the voltage between leads 107 and 108, and secondary 1 18 of transformer 1 16 provides a voltage which varies with variations in the voltage between the buses 112 and 113.

Particular reference is made now to FIGS. 3A and 3B which taken together comprise a schematic electrical circuit diagram of the converter and synchronizer shown at blocks 26 and 50, FIG. 18. Generally that part of the circuit of F 16. 3A enclosed within the dashed line designated 26' corresponds to the circuit of block 26 of FIG. 1A. Terminals 4% and 4111 are connected to the secondary of an isolation transformer generally designated 300 the primary of which is connected to leads 19 and 20. Terminals 400 and 401 have connected thereacross in series resistor 402, lead 403 and diode 4114. Terminal 4111 has a pair of parallel diodes 405 and 4116 connected therefrom to ground 24. Terminal 401 is connected by way of resistor 4117 to +50 volt lead 4118. The aforementioned lead 463 is connected to the base 410 of the transistor generally designated 411 having collector 412 and emitter 413.

Terminals 415 and 416 are connected to the secondary of an isolating transformer generally designated 3111 the primary of which is connected to bus leads 21 and 22. Terminals 415 and 416 have connected thereacross resistor 417, lead 418 and diode 419 all in series. Terminal 416 is connected by way of parallel diodes 420 and 421 to ground 24; terminal 416 is connected by way of resistor 422 to 50 volt line 4118, and lead 418 is connected to the base 423 of a transistor 424 having collector 425 and emitter 426. Emitter 426 is directly connected to ground 24. Collector 425 is connected to lead 428 which is connected to terminal 42 and is connected by way of resistor 429, lead 430, resistor 431 and lead 432 to the aforementioned collector 412 of transistor 411. Lead 432 is connected to the aforementioned terminal 41. Lead 432 and collector 412 are further connected by way of resistor 433 to lead 434 which may be of a potential +12 volts above ground. An additional parallel path exists between lead 432 and lead 428 by way of diode 436, lead 437 and diode 438. Lead 437 is directly connected to the emitter 440 of an additional transistor 441 having a base 442 and a collector 443 connected by way of lead 444 and resistor 445 to the aforementioned 50 volt lead 408. Lead 444 and collector 443 are further connected by way of diode 447 to a terminal 448 designated VB which may be at a potential +40 volts above ground. Resistor 449 is connected between base 442 and emitter 440.

The aforementioned collector 425 of transistor 424 is connected by way of resistor 451 to +12 volt supply lead 434.

Lead 444 and the aforementioned collector 443 of transistor 441 are further connected by way of series-connected inductors 453 and 454 to the base 455 of an additional transistor 456 having a collector 457 and an emitter 458. The junction between inductors 453 and 454 is connected by way of capacitor 459 and lead 460 to ground 24, and the junction between inductor 454 and base 455 is connected by way of capacitor 461 to the aforementioned lead 460 and ground 24.

Transistor 456 is connected to an additional transistor 466 to comprise a Darlington amplifier circuit, emitter 458 of transistor 456 being connected to the base 465 of transistor 466, collector 457 of transistor 456 being connected to the collector 464 of transistor 466 and both of the collectors being connected to the aforementioned 50 volt supply lead 408, while emitter 463 of transistor 466 is connected to lead 467 and further to terminal 43 for supplying a signal to the speed matcher and synchronizer, lead 467 corresponding to lead 33, FIG. 1B.

Summarizing briefly, terminal 41 of FIG. 3A may have connected thereto a lead corresponding to lead 31, FIG. 1B for supplying a squared generator signal, and terminal 42 may have connected thereto a lead corresponding to lead 32, of

FIG. 1B, for supplying a squared bus signal. Further, the two square waves of constant amplitudes but different frequencies are mixed and filtered in a portion of the circuit of FIG. 3A ineluding transistors 441, 456 and 466 and associated circuitry, so that a phase difference waveform signal, which may correspond to Curve F, FIG. 4, is obtained which signal is supplied to terminal 43, which may connect to lead 33, FIG. 1B.

The aforementioned lead 434, which may correspond to the lead 35, FIG. 1B, is seen to be connected by way of resistor 470 and lead 471 to the emitters 472 and 473 of a pair of transistors generally designated 474 and 475 having collectors 476 and 477 respectively and bases 478 and 479 respectively. Collector 476 is directly connected to aforementioned lead 460, whereas collector 477 is connected by way of lead 496 and resistor 480 to lead 460. Base 478 of transistor 474 is connected by way of lead 481 and resistor 482 to the aforementioned lead 467. Diode 483 interconnects emitter 472 and base 478, while resistor 482 has capacitor 484 connected thereacross. The aforementioned lead 481 has resistor 485 connected therefrom the lead 460.

As previously stated in connection with FIG. 1A, the synchronizer controls include a breaker closing time control, which may be calibrated from 0.10 to 0.20 seconds, and a multiplier therefor, which may give X1, X2, and X4. To this end, potentiometer 380 and resistor 382 in series therewith are connected between leads 467 and 460. The potentiometer has arm 381 thereof connected to one arm 383 of a double pole, triple throw switch having an additional arm 384 ganged to arm 383 for movement therewith. Arm 383 has contacts 385, 386 and 387 associated therewith, while arm 384 has contacts 388, 389, and 390 associated therewith. Contact 385 is connected to arm 384 and to one terminal of capacitor 391 which has the other terminal connected to contacts 386 and 387, which are connected to one terminal of capacitor 392 which has the other terminal connected to lead 481. Capacitors 391 and 392 may be 2 microfarads each. In accordance with the setting of the switch, arm 38] of potentiometer 380 is connected by way of a capacity of l microfarad, 2, or 4 microfarad, to lead 481.

Diode 486 is connected between emitter 473 and base 479 of transistor 475. The aforementioned base 479 of transistor 475 is connected by way of lead 488 and resistor 489 to +40 volt lead 686. The lead 488 is further connected by way of resistor 491, lead 492 and resistor 493 to the aforementioned lead 434. Lead 488 is still further connected by way of variable resistor 494 and resistor 495 to aforementioned lead 460.

The aforementioned collector 477 of transistor 475 is connected by way of lead 496 and resistor 497 to the base 498 of a further transistor generally designated 499 having a collector 500 directly connected to the aforementioned lead 492, and having an emitter 501 directly connected to the aforementioned lead 460. The aforementioned lead 496 is also connected by way of resistor 502 and lead 503 to the base 504 of a further transistor generally designated 505 having an emitter 506 directly connected to lead 460 and having a collector 507 connected by way of resistor 508 to the aforementioned lead 434. Collector 507 is further connected by way of series connected resistor 509 and capacitor 510 to lead 460, and the junction between resistor 509 and capacitor 510 is further connected to the base 512 of a still further transistor generally designated 513 having emitter 514 thereof directly connected to lead 460 and having the collector 515 thereof connected by way of lead 516 and resistor 517 to the aforementioned lead 434. Base 512 has resistor 518 connected therefrom to lead 460, and base 512 is further connected by way of resistor 520, lead 521 and resistor 522 to the aforementioned lead 434.

A still further transistor generally designated 524 includes a collector 525 connected to the aforementioned lead 521, an emitter 526 connected to the aforementioned lead 460, and a base 527 connected by way of resistor 528 to the aforementioned lead 516. Base 527 is further connected by shunt capacitor 529 and resistor 530 to lead 460, and base 527 is further connected by way of resistor 532 to lead 533 to form a further circuit portion to be traced in detail hereinafter.

An additional pair of transistors 535 and 536 have emitters 537 and 538 thereof respectively connected together and connected by way of resistor 539 to lead 540 and terminal 541, connected to +1.2 volt lead 434. The base 543 of transistor 535 is connected by way of resistor 544 to the aforementioned lead 467, and the collector 545 of transistor 535 is connected to lead 546 and thence to ground 24. Resistor 547 is connected between lead 546 and the aforementioned base 543.

The collector 550 of transistor 536 is connected by way of resistor 551 to the aforementioned lead 546 and is also directly connected to the base 553 of an additional transistor generally designated 554 having a collector 555 connected by way of resistor 556 to the aforementioned lead 540, and having an emitter 557 directly connected to lead 546.

The aforementioned transistor generally designated 536 also has a base 542 connected to the arm 560 of a potentiometer 561 having one end thereof connected by way of resistor 562 to lead 546, and having the other end thereof connected by way of variable resistor 563 and resistor 564 to lead 686 which may be at a potential +40 volts above ground. A diode 565 is connected from arm 560 to the emitters 537 and 538, and the aforementioned am 560 is connected by way of resistor 566 and lead 533 and resistor 567 to the aforementioned lead 503 and the base 504 of transistor 505.

From the aforementioned lead 540, resistors 571 and 572 connect the lead by way of leads 573 and 574 to the collectors 575 and 576 of a pair of additional transistors 577 and 578 respectively having emitters 579 and 580 respectively directly connected to lead 546 with the base 581 of transistor 577 being connected by way of lead 582 and resistor 583 to the aforementioned lead 574. The base 585 of transistor 578 is connected by way of lead 586 and resistor 587 to the aforementioned lead 573.

The aforementioned lead 582 connected to base 581 is connected by way of a parallel capacitor 588 and resistor 589 to lead 546. Lead 586 connected to base 585 is connected by way of parallel resistor 590 and capacitor 591 to lead 546. Further lead 586 is connected by way of resistor 592, diode 593 and resistor 594 to lead 546. The junction between diode 593 and resistor 594 is connected by way of capacitor 595,

.lead 596 and resistor 597 to lead 546.

The aforementioned base 581 of transistor 577 and lead 582 connected thereto are connected by way of resistor 599 to lead 600 and thence directly to the collector 601 of an additional transistor 602, the purpose of which will become hereinafter more clearly apparent. The lead 600 is connected by way of diode 604 and resistor 605 to lead 503 and the base 504 of transistor 505. The aforementioned lead 582, connected to the base 581 of transistor 577, is connected by way of resistor 599 to lead 600.

An additional transistor 610 is shown having a base 611, collector 612 and emitter 613 directly connected to lead 546. Base 611 is connected by way of resistor 615 to lead 546, and base 611 is connected by way of resistor 616 to lead 617 which is shown connected to the cathodes of five diode rectifiers 621 to 625 inclusive. The anode of diode 621 is connected to lead 516; the anode of diode 622 is connected to lead 492; the anode of diode 623 is connected to lead 573; and the anode of diode 624 is connected to the aforementioned lead 600. The anode of diode 625 is connected by way of lead 626 to a terminal 627.

With reference to diode 625, in the aforementioned copending application of Tibor Rubner for Voltage Acceptor Circuit And Overvoltage-Undervoltage Detector for Use Therein," there are shown two embodiments. in one of these embodiments when the generator and line voltages are sufiiciently close to a selected center voltage and close to each other, so that synchronization is possible and a generator may be connected in parallel with the bus under those conditions the final output transistor conducts in said one embodiment. When the voltages are not within the required range for synchronization the voltage supply develops a voltage on the output lead and the collector of the final transistor, and this output voltage would be applied by way of terminal 627 and lead 626 to diode 625, and current would flow therethrough with the result, as may be explained in more detail hereinafter, that this voltage on lead 626, when the output transistor of the overvoltage-undervoltage detector is blocked and conditions for synchronization are not favorable, this output voltage passing through diode 625 and operative on the aforementioned transistor 610 prevents output transistor 630 from saturating and therefore output relay 56 and aforementioned circuit breaker 100 of FIG. lB cannot be energized.

In the other embodiment of the overvoltage-undervoltage detector shown in the aforementioned copending patent application, the final or output transistor is saturated when conditions exist so that synchronization is undesirable. That other embodiment has the output terminal connected to terminal 632, which is connected by way of lead 633 across capacitor 634; the saturated current path through the transistor effectively places a short circuit or shunt circuit through a low resistance across the capacitor 634, bleeding the charge therefrom, with the result that transistor 602 is blocked, diode 624 is forward biased rendering transistor 610 conductive, and output transistor 636 blocked, keeping output relay 56 deenergized thus preventing synchronization.

Capacitor 634 is used as a timing device for preventing synchronization or paralleling for one second after the circuit is first energized.

It will be apparent then that a signal from the overvoltageundervoltage detector is applied to either terminal 627 or terminal 632 in accordance with the embodiment employed, but that no one signal is applied to both these terminals, and no two signals are applied to them simultaneously.

Diode 625 and lead 626 may be dispensed with where a signal is applied to terminal 632.

The aforementioned transistor generally designated 630 has a base 631 directly connected to collector 612 of transistor 610, said base also being connected by way of resistor 636 to a power supply lead or terminal identified as VA which it is seen has a voltage of 12 volts appearing thereacross at lead 434 the voltage being obtained at the junction of resistor 640 and Zener diode 639. Lead 434 and Zener diode 639 are connected to the 50 volt supply lead 408 by way of resistor 640.

The aforementioned transistor generally designated 630 has an emitter 641 directly connected to lead 546 and a collector 642 connected by way of relay winding 55 of relay 56, lead 644, resistor 645, and lead 646 to terminal 647 which is connected to lead 52 of FIG. 1B. Armature 120 of relay 56 when closed completes the circuit between terminals 802 and 803 which may be connected to ground and the circuit breaker winding respectively as shown in FIGS. IA and 1B. Armature 120 of relay 56 thus initiates synchronization, or paralleling when relay 56 is energized. Armature 57 of relay 56 when closed completes the circuit between terminals 864 and 865 which terminals are connected as shown in FIG. 1B. Arma' tures 57 and 120 move together. Diode 648 is connected between collector 642 and lead 644, and capacitor 649 is connected between lead 546 and lead 644.

The aforementioned transistor generally designated 602 in addition to collector 601 has a base 651 and an emitter 652 directly connected by way of lead 653 to ground 24. Base 651 is connected by way of resistor 655 and Zener diode 656 to the aforementioned lead 633 and terminal 6322. Lead 633 is connected by way of resistor 658 to the aforementioned 50 volt supply lead 468. Capacitor 659 is connected from base 631 to lead 653. The aforementioned collector 6011 in addition to being connected to the aforementioned lead 600 is connected by way of resistor 660 to the 12 volt lead 434.

The aforementioned 50 volt supply lead 468 is connected by way of resistor 662 and capacitor 663 to lead 653. The junction between resistor 662 and capacitor 663 is connected by way of a Shockley diode 664, resistor 665, diode 666, capacitor 667, and diode 663. to the emitter 670 of a unijunction transistor having bases 67! and 672. The junction between diode 666 and capacitor 667 is connected by way of resistor 673 to lead 653. The junction between capacitor 667 and diode 668 is connected by way of resistor 675 to the aforementioned lead 596 which has capacitor 676 connected therefrom to ground and which is connected by way of resistor 677 and lead 676 to terminal 679 which is connected to lead 51 of FIG. 1B.

The aforementioned emitter 670 of the unijunction transistor $06 is connected by way of resistor 681 to 12 volt supply lead 434, and base 671 is connected by resistor 682 to the aforementioned 12 volt supply lead 434. The base 672 is connected by way of resistor 683 to ground 24, and the base 672 is connected by Way of diode 684 to the aforementioned lead 582 and base 581 of transistor 577.

The aforementioned power supply terminal identified as VB has a positive potential of 40 volts with respect to ground thereacross, and is obtained at the junction of resistor 687 and series-connected diode6fl8 and Zener diode 639.

In the portion of the converter schematic electrical circuit diagram of FIG. 3A which contains the switching circuitry and filters employed for developing a phase difference waveform on lead 467 and at terminal 43, transistors 411 and 424 and their associated circuits produce symmetrical square waves of generator and bus frequency respectively, in accordance with FIG. 4, although it will be understood that they could be oppositely connected if desired. The output signals of these transistors, which could be designated j}, and f as shown in FIG. 4 are fed to an exclusive NOR gate for mixing; the exclusive NOR gate which may include transistor 441 and associated circuitry operates in the following way: when both j}, and f are logical ones, that is, they are positive, transistor 441 will block and give a logical one output, since diodes 438 and 436 are reverse biased. When both f and f are logical zeros, that is, they are at ground potential, transistor 441 again blocks (produces a logical one output) since it has no base drive. When either of the signals (f f is a logical one while the other is a logical zero, transistor 441 will saturate, since base drive is provided either through resistor 431 or resistor 429. and either diode 438 or diode 436 is forward biased. The output is now a logical zero.

Particular reference is made now to FIGS. 2A and 28, diagrams of the synchronizer shown in schematic electrical circuit diagram in FIGS. 3A and 3B.

The sinusoidal bus and generator voltages, obtained from the potential transformers are coupled via isolating transformers 3M! and 301 to pulse shapers 69B and 692 respectively. These sinusoidal voltages are represented by waveforms A and B respectively of FIG. 4. The output of pulse shaper 691 is a square wave of constant amplitude having the frequency of the bus voltage, and may be represented by the waveform C of FIG. 4. The output of pulse shaper 692 is a square wave of constant amplitude having the frequency of the generator voltage, and may be represented by the waveform D of FIG. 4. The outputs of pulse shapers 65 1 and 692 are mixed by transistor 4411 and associated circuitry in the circuit of FIG. 3A, the resulting waveform being shown by waveform E of FIG. 4. After mixing, filtering is applied and the waveform F of FIG. 4 results, which is proportional to the average amplitude of Curve E. The mixing and filtering functions are performed by the block designated 693 which may include transistor 44K and associated circuitry, a low pass filter consisting of inductors 453, 454, capacitors 453 and 46B, and Darlington circuit composed of transistors 456 and 466. The output of mixer and filter block 693 is thus a triangular voltage of constant amplitude, its frequency being equal to the difference in frequency between the bus and generator voltages. The instantaneous value of the voltage output of block 693 is thus proportional to the instantaneous phase difference between the bus and generator voltages. In this particular embodiment the maximum value of the triangular voltage waveform corresponds to zero degrees phase shift. The triangular voltage output of the block 633, hereinafter referred to as the phase difference waveform and shown by waveform F of FIG. 4 is applied to level detector 694 which produces an output as long as the phase difference waveform exceeds a certain predetermined,

adjustable level. Thus, level detector 694 which may include transistors 535, 536, and 554 and associated circuitry can produce an output at a definite phase relationship of the bus and generator voltages. This last-named output may be referred to herein as the phase advance angle signal. The output begins when there is a certain phase relationship and ends when there is a certain phase relationship in accordance with the adjustment of the threshold being set by potentiometer 561. The output of block 693, i.e., the waveform F of FIG. 4 is also applied to a differentiator 695 which may include capacitors 391, 392, resistors 485, 382, potentiometer 380 and capacitor 484. The output of the differentiator is thus a square wave, whose amplitude is proportional to the frequency of the phase difference waveform, i.e., it is proportional to the frequency difference between the bus and generator voltages. The constant of proportionality is adjustable by potentiometer 380 and the switch having arms 383 and 384 and is used to accommodate different breaker closing times. The output of differentiator 695 is not shown in FIG. 4. Block 699 represents a summing operation, so it can be seen that the outputs of block 693 and block 695, i.e., the phase difference waveform and its first derivative are added together algebraically. The output of block 699, i.e., the sum of the phase difference waveform and its first derivative is shown by waveform G of FIG. 4, and is applied to a second level detector or discriminator 696 which may include transistors 472 and 473 and associated circuitry. The amplitude of waveform G of FIG. 4 is not constant but depends on the frequency difference between the bus and generator voltages and the adjustment of the differentiator. The threshold level of level detector 696 is adjusted by variable resistor 494 to a voltage that corresponds to the value of waveform G of FIG. 4 when the bus and generator have equal frequencies, it being understood that waveform G is necessarily a DC level when the frequency difference is zero. IT can be shown mathematically that the output of level detector 696 will occur at a definite time before phase coincidence of the bus and generator voltages, independent of the frequency difference between them. This definite time can be adjusted to correspond to the desired breaker closing time by the aforementioned adjustment of the differentiator. Thus the output of level detector 694 begins at a definite phase before phase coincidence of the bus and generator voltages and the output of level detector 696 begins at a definite time before phase coincidence corresponding to the threshold level of level detector 694. Depending on the frequency difference, the output of level detector 694 can begin before or after the output of level detector 696 begins. Generally, the output of level detector 696 appears first if the frequency difference is too high. Thus there is needed some means for determining which of the two level detectors produces an output first, i.e., whether the frequency difference is too great or not. If the frequency difference is too great, synchronization is prevented and if it is not too great, synchronization is initiated at the instant an output appears on lead 702. This decision making is performed by the logic circuitry 697, which is shown in more detail in FIG. 2A. When a signal is present on lead 701 but not on lead 702, i.e., the output of level detector 694 occurs first, both inputs of AND-gate 703 whose function may be equivalently performed by transistor 505 and associated circuitry will have signals present and it will set the bistable circuit 705 which may include transistors 513 and 524 and associated circuitry. The bistable circuit will remain set as long as an output from level detector 694 is present. Thus when a signal appears on lead 702 corresponding to the output of level detector 696 it can go through the AND-gate 708 whose function may be equivalently performed by transistors 610 and 630, diodes 621, 622, and 623 and associated resistors and energize the circuit breaker, i.e., paralleling or synchronization can take place. The bistable circuit 705 is reset as soon as the signal on lead 701 ceases, which occurs at a definite phase after phase coincidence. If the signal on lead 702 occurs before the signal on lead 701, i.e., the frequency difference is too great, the bistable circuit cannot be set as long as the signal on lead 702 is present. Thus synchronization cannot take place, since the signal on lead 737 corresponding to the bistable circuit being set, and the signal on lead 702 do not overlap. Timer 698 which may include unijunction transistor 806 and associated circuitry in conjunction with bistable circuit 710 which may include transistors 577 and 578 and associated circuitry form a breaker antipump circuit. After paralleling has taken place and the circuit breaker closes, a normally open auxiliary contact of the circuit breaker, connected to lead 712 which lead corresponds to terminal 679 of FIG. 3A and lead 51 of FIG. 1B, sets bistable circuit 710 and at the same time initiates the timing periods of the timer, which may be 10 seconds. As long as bistable circuit 710 is set synchronization cannot occur as will be obvious to those skilled in the art. If the circuit breaker remains closed for a sufficient time the timer can time out and reset bistable circuit 710, and synchronization can again occur. However, if the circuit breaker opens before the timer had a chance to time out, the bistable circuit 710 cannot be reset and synchronization will be prevented.

Certain further explanation of our invention of a mathematical nature appears in a paper titled A High Accuracy Automatic Generator Synchronizing System by T. D. Rubner, A Wavre, and J. Bednarek, presented at the IEEE Summer Power Meeting, July 9-l4, 1967, Paper No. 31 CP 67-488.

We claim as our invention:

1. In apparatus for obtaining a signal at a selected phase relationship between two alternating current voltages of different frequencies, in combination, circuit means adapted to have first and second alternating current voltages of different frequencies applied thereto, said circuit means producing first and second square waves having frequencies corresponding to those of the first and second alternating current voltages respectively, other circuit means having the first and second square waves applied thereto and producing an output rectangular waveform obtained by combining the first and second square waves, further circuit means having the output rectangular waveform applied thereto and producing a triangular beat frequency signal having a linear relationship between phase difference and time, a level detector having the triangular beat frequency signal applied thereto, said level detector producing said first-named signal when the triangular beat frequency signal exceeds in amplitude a selected adjustable level in the level detector, summing circuit means having the triangular beat frequency signal having a linear relationship between phase difference and time applied thereto, differentiator means having the triangular beat frequency signal applied thereto, means for applying the output of the differentiator means to the summing circuit means to obtain a further waveform representing the algebraic sum of the triangular beat frequency signal and its first derivative, and a further level detector having the further waveform applied thereto as an input, said further level detector producing an output while the input thereto is above a selected, adjustable level in the further level detector.

2. Apparatus according to claim 1 in which the instant when the output of the first-named level detector starts represents a definite phase relationship between the first and second alternating current voltages, and the output of the further level detector occurs at a definite time before phase coincidence of the bus and generator voltages independent of the frequency difference between them, and including in addition logic circuitry having the output of the first-named level detector and the output of the further level detector applied thereto as inputs.

3. Apparatus according to claim 2 in which the logic circuitry includes a first AND circuit and a first NOT circuit both having the output of the first named level detector applied thereto, a second AND circuit and a second NOT circuit both having the output of the further level detector applied thereto, means applying the output of the second NOT circuit as an input to the first AND circuit, a bistable circuit operatively connected to the first AND circuit to be set by an output of all,

connected to the first NOT circuit to be reset by an output of i the first NOT circuit, and means connecting the second AND circuit to the bistable circuit to receive an input from the bistable circuit while the bistable circuit is in set condition, said second AND circuit when all inputs are simultaneously present thereat producing an output adapted to be utilized to close a circuit breaker.

4. Apparatus according to claim 3 in which the second AND circuit has an additional third input, and including in addition a further bistable circuit operatively connected to the second AND circuit to supply a third input thereto while the further bistable circuit is in a selected stable state.

5. Apparatus according to claim 4 in which the further bistable circuit has first and second input means adapted to receive signals to cause the further bistable circuit to assume set" and reset stable states, and timer means connected between the first and second input means, said timer means resetting the logic circuitry after a predetermined interval of time.

6. ln apparatus for obtaining a signal at a selected phase relationship between two alternating current voltages of different frequencies, in combination, circuit means adapted to have first and second alternating current voltages of different frequencies applied thereto, said circuit means producing first and second square waves having frequencies corresponding to v those of the first and second alternating current voltages respectively, other circuit means having the first and second square waves applied thereto and producing an output rectangular waveform obtained by combining the first and second square waves, further circuit means having the output rectangular waveform applied thereto and producing a triangular beat frequency signal having a linear relationship between phase difference and time, a level detector having the triangular beat frequency signal applied thereto, said level detector producing said first-named signal when the triangular beat frequency signal exceeds in amplitude a selected adjustable level in the level detector, an additional circuit means for obtaining a different function of said triangular beat frequency signal, a summing circuit for obtaining an output which is the algebraic sum of said amplitude and said different function of said triangular beat frequency signal, and an additional level detector which is responsive to said algebraic sum for producing an output when said algebraic sum exceeds a selected level. 

1. In apparatus for obtaining a signal at a selected phase relationship between two alternating current voltages of different frequencies, in combination, circuit means adapted to have first and second alternating current voltages of different frequencies applied thereto, said circuit means producing first and second square waves having frequencies corresponding to those of the first and second alternating current voltages respectively, other circuit means having the first and second square waves applied thereto and producing an output rectangular waveform obtained by combining the first and second square waves, further circuit means having the output rectangular waveform applied thereto and producing a triangular beat frequency signal having a linear relationship between phase difference and time, a level detector having the triangular beat frequency signal applied thereto, said level detector producing said first-named signal when the triangular beat frequency signal exceeds in amplitude a selected adjustable level in the level detector, summing circuit means having the triangular beat frequency signal having a linear relationship between phase difference and time applied thereto, differentiator means having the triangular beat frequency signal applied thereto, means for applying the output of the differentiator means to the summing circuit means to obtain a further waveform representing the algebraic sum of the triangular beat frequency signal and its first derivative, and a further level detector having the further waveform applied thereto as an input, said further level detector producing an output while the input thereto is above a selected, adjustable level in the further level detector.
 2. Apparatus according to claim 1 in which the instant when the output of the first-named level detector starts represents a definite phase relationship between the first and second alternating current voltages, and the output of the further level detector occurs at a definite time before phase coincidence of the bus and generator voltages independent of the frequency difference between them, and including in addition logic circuitry having the output of the first-named level detector and the output of the further level detector applied thereto as inputs.
 3. Apparatus according to claim 2 in which the logic circuitry inCludes a first AND circuit and a first NOT circuit both having the output of the first named level detector applied thereto, a second AND circuit and a second NOT circuit both having the output of the further level detector applied thereto, means applying the output of the second NOT circuit as an input to the first AND circuit, a bistable circuit operatively connected to the first AND circuit to be set by an output of the first AND circuit, said bistable circuit being operatively connected to the first NOT circuit to be reset by an output of the first NOT circuit, and means connecting the second AND circuit to the bistable circuit to receive an input from the bistable circuit while the bistable circuit is in set condition, said second AND circuit when all inputs are simultaneously present thereat producing an output adapted to be utilized to close a circuit breaker.
 4. Apparatus according to claim 3 in which the second AND circuit has an additional third input, and including in addition a further bistable circuit operatively connected to the second AND circuit to supply a third input thereto while the further bistable circuit is in a selected stable state.
 5. Apparatus according to claim 4 in which the further bistable circuit has first and second input means adapted to receive signals to cause the further bistable circuit to assume ''''set'''' and ''''reset'''' stable states, and timer means connected between the first and second input means, said timer means resetting the logic circuitry after a predetermined interval of time.
 6. In apparatus for obtaining a signal at a selected phase relationship between two alternating current voltages of different frequencies, in combination, circuit means adapted to have first and second alternating current voltages of different frequencies applied thereto, said circuit means producing first and second square waves having frequencies corresponding to those of the first and second alternating current voltages respectively, other circuit means having the first and second square waves applied thereto and producing an output rectangular waveform obtained by combining the first and second square waves, further circuit means having the output rectangular waveform applied thereto and producing a triangular beat frequency signal having a linear relationship between phase difference and time, a level detector having the triangular beat frequency signal applied thereto, said level detector producing said first-named signal when the triangular beat frequency signal exceeds in amplitude a selected adjustable level in the level detector, an additional circuit means for obtaining a different function of said triangular beat frequency signal, a summing circuit for obtaining an output which is the algebraic sum of said amplitude and said different function of said triangular beat frequency signal, and an additional level detector which is responsive to said algebraic sum for producing an output when said algebraic sum exceeds a selected level. 